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semiconductor technical data 1 rev 0 ? motorola, inc. 1997 7/97 ? ? ! the mc100sx1451fi100 autobahn chip is a highspeed serial toparallel, paralleltoserial transceiver. the autobahn can be used to implement a highspeed, halfduplex, bidirectional serial data link with an effective data transfer rate of 100mbyte/sec. a higher performance autobahn chip, with user selectable serial data transfer rates of 100 or 200mbyte/s, is planned (see the mc100sx1451fi200 datasheet).this serial link can be used to establish multipoint or pointtopoint connections. a unique differential cutoff driver switches from a standard pecl v oh level to cutoff. in the cutoff state the outputs present a high impedance which is required to implement a true shared bus. the part features a 32bit wide parallel ttl compatible i/o interface that can connect directly with standard memory or bus transceiver devices. the control pins are all ttl compatible to simplify interfacing requirements. the serial interface is pecl (positive emitter coupled logic) which provides excellent transmission line drive capability. because the serial bus is implemented using differential ecl technology, the receiver circuitry exhibits excellent common mode noise rejection. ? 100mbyte/s serial data transfer capability ? ttl compatible parallel interface ? supports 16 or 32bit data bus interfaces ? bus driving differential ecl serial outputs ? onboard clock recovery and data synchronization ? 64pin surface mount cqfp packaging ? parallel data bus handshake control an innovative data synchronizing architecture allows data to be transmitted in bursts without preamble bits. this allows instantaneous data acquisition without the inherent overhead of traditional pll clock recovery. thus, the data transfer is nearly overhead free with only one synchronization bit for every byte of data transmitted. insertion and removal of synchronization bits are totally transparent to the user. the autobahn supports variable data transfer rates. this is accomplished by combining the fixed burst transfer rates of 50 or 100mbyte/s with a flexible method of allowing data to be written into the autobahn for transfer. if new data has not been written into the parallel data register prior to the completion of a serial data burst, the autobahn will insert a gap in the serial data stream. therefore, the effective throughput of the serial bus is throttled by the speed of the parallel host interface which writes data to the chip. with its very high block data transfer capability and instantaneous start up ability, the autobahn is ideally suited for multimedia graphics applications and parallel processing architectures requiring multiprocessor communication links. motorola's stateoftheart mosaic v ? process allows for the realization of 1.8ghz internal clock rates at power levels which are compatible with today's low profile surface mount packages. furthermore, the design is implemented with a flowthrough pinout architecture to simplify pcb layout and routing. the board space efficiency of the cqfp ensures that the autobahn device will prove valuable in the most demanding space conscious applications. the autobahn chip works from a single +5.0v supply. separate internal v cc busses isolate the ttl outputs from the high speed pecl circuitry. autobahn and spanceiver are trademarks of pep modular computers. `spanceiver' has been formed as a contraction of serial/parallel transceiver. mosaic v is a trademark of motorola, inc.
autobahn ? spanceiver ? fi suffix ceramic qfp package case 96302
mc100sx1451fi100 motorola eclinps and eclinps lite dl140 e rev 3 2 control register error register figure 1. simplified block diagram transmit register piso shift register sync bit generator receive register sipo shift register sync bit extract pll clock generator differential detector piso control logic sipo control logic serial bus transceiver full busy error fosc c1 d31 d00 regsel register read/ write logic reset logic r/w strb reset ser ser
mc100sx1451fi100 eclinps and eclinps lite dl140 e rev 3 3 motorola pin descriptions name i/o description ttl compatible i/o reset i asynchronous reset signal which places the autobahn into default state. in most applications, reset should only have to be asserted on system startup. r/w i read/write control signal. used to select between writing to or reading from the autobahn. regsel i control signal used to select between the parallel data register and the control and error register(s). a logic `h' selects the data register while a logic `l' selects the control and error register(s). d00 d31 i/o bidirectional data inputs/outputs. these pins comprise the data bus to be used to interface to the user host interface. d00 is the least significant bit. strb i data strobe signal. during a write, it indicates that data is valid on the parallel bus. while in a read, it indicates that the autobahn can now place data on the parallel interface. full o signal which indicates that the transmitter or receiver presently contains data. in conjunction with the strb signal, it is used to implement a two signal handshake for parallel data transfers. busy o serial bus busy signal, used to indicate to the parallel interface that the autobahn bus is presently in use. error o control output which is used to indicate that the autobahn has identified a fault condition. the error condition can then be read out from the error register. fosc i 25.00mhz clock source from a crystal oscillator reference. pecl compatible i/o ser/ser i/o differential serial data inputs/outputs which operate at modified pecl levels. power, ground and filter pins name number description c1 1 pll filter capacitor pin v cce 1 positive supply for internal pecl logic circuitry v cco 1 positive supply for pecl outputs v ee 1 ground for pecl v cct 7 positive supply for ttl compatible signals v eet 8 ground for ttl compatible signals v ccx 1 positive supply for vco v eex 1 ground for vco block diagram functional description reset logic the reset logic generates the internal reset signal used to set the device into a known state. the reset signal clears the control and error registers and resets the sipo and piso control logic. the external reset signal is validated with the fosc input clock to assure that a valid reset pulse has been applied to the chip. the external reset input pin (reset ) must be low for a minimum of 125 nsec after the fosc input is stable. strb assertion may occur no earlier than 500 nsec after reset deassertion (reset recovery time). control register the control register is used to configure the operation of the autobahn. the register fields are described in detail in the section containing the control and error register bit definition. register read/write control logic this logic is utilized to access the transmit register, the receive register, and the control and error registers from the parallel bus. the interface protocol utilizes two direction control signals (r/w and regsel). the actual handshake to
mc100sx1451fi100 motorola eclinps and eclinps lite dl140 e rev 3 4 read or write data from the chip is accomplished with the input strb signal , combined with the output full signal. transmit register the transmit register is a 32bit wide parallelloadable register. this register interfaces to the bidirectional ttl compatible data bus. access to this register is controlled via the register read/write logic. piso shift register the piso (parallel in/serial out) register accepts data from the transmit register and converts it into a serial bit stream. this register is under control of the piso control logic. the shift register can be adjusted to handle 16bit or 32bit data traffic based on the state of the appropriate field in the control register. piso control logic the piso (parallel in/serial out) control logic is responsible for controlling the transfer of data out from the autobahn to the serial bus. this logic interfaces to the piso shift register and the sync bit generator. it is driven by the pll clock generator. sync bit generator this circuitry inserts one bit of timing information into the data stream before every byte of data is sent to the serial bus transceiver and transmitted. this timing information is used by the receiver to properly reclock the incoming data stream. to support the maximum data rate of 100 mbyte/sec, the actual serial shift rate is 900 mbit/s nrz, rather than 800 mbit/s nrz. the insertion and removal of sync bits is transparent to the end user. serial bus transceiver the transceiver implements a two signal bidirectional differential bus. the transceiver circuitry consists of a highly sensitive differential receiver and a cutoff driver. the receiver accepts a differential signal from the serial bus. this differential signal is amplified and limited by the receiver before being routed to the clock generation circuitry for clock extraction and data retiming. the cutoff driver is used to transmit serial data on to the bus. the outputs switch between a normal high level (v oh ) and a cutoff low signal when low the output emitter follower is turned 'off', thus presenting a high impedance to the bus. if the cutoff driver is disabled, both outputs of the differential pair go to the cutoff state so the bus resource is available for use by other autobahn chips sharing the same bus. differential detector the differential detector is used to recognize when the serial bus goes out of the cutoff state and into a differential steady state condition. the differential detector is only utilized at the very start of a transmission. the detector informs the sipo control logic that the serial bus is no longer in cutoff so that the bus busy signal can be asserted by the device. pll clock generator the clock generator circuitry synthesizes a master timing clock from the frequency reference signal (fosc) input. the clock generator provides timing signals used to support the transfer rate of 900 mbit/s. the clock is generated by a phase locked loop (pll) which requires a simple external capacitor to set the loop filter bandwidth. the value for c1 is 2700 pf. this circuitry is used to provide the master timing for the piso and sipo control logic blocks. sync bit extractor the sync bit extractor removes each sync bit from the incoming data stream. it is controlled by the sipo control logic. if a sync bit is not detected at the proper bit time in the extraction process, a field will be set in the error register to indicate that a transmission error has occurred. sipo shift register the sipo (serial in/parallel out) register accepts data from the sync bit extractor and converts it into a parallel word that is then transferred to the receive register. the operation of this shift register is controlled by the sipo control logic. sipo control logic the sipo (serial in/parallel out) control logic is responsible for controlling the transfer of data into the autobahn. this circuitry performs all the critical control functions to allow the autobahn to accept and process the incoming serial data stream. the sipo control logic has the ability to detect certain transmission related errors and set the appropriate field(s) in the error register. receive register the receive register is a 32bit wide parallel load register. it accepts data from the sipo (serial in/parallel out) shift register. this register interfaces to the bidirectional ttl compatible data bus. access to this register is controlled via the register read/write logic. error register the autobahn has the capability to detect certain transmission related error conditions. these errors are detected by the sipo control logic which sets the appropriate error field in the error register. the register fields are described in detail in the section containing the control and error register bit definition. the error register has additional logic that is used to generate the error signal.
mc100sx1451fi100 eclinps and eclinps lite dl140 e rev 3 5 motorola differential ser detected figure 2. transmit and receive state diagram ser (serial data) in cutoff new data written into transmit register ser differential, waiting for 15ns 15ns timer expired no new data written into transmit register new data written into transmit register new data written into transmit register reset 4 longword timer expired autobahn transmit state diagram waiting for differential ser [assert busy signal] waiting for start bit start bit observed receiving serial data words no new start bit observed new start bit observed new start bit observed reset autobahn receive state diagram waiting four longword periods since latest start bit 4 longword timer expired [negate busy signal] waiting for 10ns transmitting serial data words waiting four longword periods since latest start bit 10ns timer expired theory of operation and transmit timing principle the autobahn is a high speed data mover resource for use in parallel bus systems, such as the vmebus. it is also suitable for proprietary bus architectures and pointtopoint links. all necessary logic, such as multiplexing/ demultiplexing, control, and timing generation is incorporated on chip. external control signals and a frequency reference must be provided to the device. arbitration is off loaded to the parallel bus system; thus, no collision detection or protocol overhead is required for the chip. the autobahn has three primary operating modes: idle transmit receive figure 2 has been included to aid in understanding the operation of the device. idle mode after the device has been reset, the default operating mode is idle. in the default condition the serial bus is cut off and the receiver is 'listening' to detect activity on the serial bus. the function of this mode is to detect serial bus activity and assert a busy signal. in a vme type application, this signal is used by the local controller to determine when to arbitrate for the serial bus resource. transmit mode to begin a transfer, data is written into the parallel data register. this event starts an internal timeout timer. the autobahn transfers the data to the serial transmit register, inserts timing information, and shifts the data out the serial bus. the timing information adds one additional bit into the data stream for every byte of data. because the data is nrz, a 900mbit/s data rate translates into a maximum frequency of 450mhz. if a new word has been loaded into the parallel data register, the next transfer will begin. otherwise, the differential output driver will hold the serial bus at the state of the last data bit transmitted. the bus will be held in this state until new data is loaded into the parallel data register or the timeout time expires. the timeout timer runs for a period of four 32bit transfer times. the transfer rate is selected through control register select bits. as an example, in 32bit mode with a transfer rate
mc100sx1451fi100 motorola eclinps and eclinps lite dl140 e rev 3 6 of 100mbyte/s, a new data word is transferred approximately every 40ns (32 data bits + 4 synchronization bits = 36 bits * 1.1ns/bit). for this case, the timeout timer runs for approximately 160ns. the timeout timer is restarted every time a new serial word transmission begins. the transmit timeout timer serves two functions. it allows the termination of block data transfers without the need for explicit external control. after the last word in a data block is written into the device, the timeout timer will expire and the device will return to the idle state. more importantly, it allows the autobahn to support a broad range of data transfer rates. if a hardware design application only needs capacity to transfer data at 60mbyte/s, the autobahn will automatically burst the data out at 100mbyte/sec and insert pauses in the serial data stream to accommodate the slower parallel data transfer rate. this means the user can tailor the design of the parallel memory interface to meet the needs of the application, while still taking advantage of the performance of the autobahn. since the autobahn only has one level of elastic storage, the receiver memory interface must be able to support the same transfer rate as the transmitter. receive mode when the autobahn is operating in receive mode it strips off the timing information and clocks the data into the serial register. when the register is full, it transfers the data into the parallel data register and asserts the full signal pin to indicate the presence of data. the interface hardware detects the presence of new data and reads out the content of the data register. in receive mode, a timeout timer is also employed to handle the end of data transfer termination. the receive timeout timer operates in the same manner as the transmit timeout timer. every time new data is received, the timeout timer is restarted. if no data is received, the timeout timer will expire and the part will return to the idle state. typical data transmission waveforms are shown in figure 3 and figure 4. figure 3. transmit and receive timing for a single 32bit longword transmissions regsel d00:d31 r/w strb full ser busy write data timeout delay d31 sync d0 d1 d2 d3 cutoff cutoff transmitting autobahn regsel d00:d31 r/w strb full ser busy read data timeout delay d31 cutoff cutoff receiving autobahn sync d0 d1 d2 d3
mc100sx1451fi100 eclinps and eclinps lite dl140 e rev 3 7 motorola figure 4. transmit and receive timing for burst transmission regsel d00:d31 r/w strb full ser busy write data 36bit serial cutoff transmitting autobahn regsel d00:d31 r/w strb full ser busy receiving autobahn write data write data write data write data 36bit serial 36bit serial 36bit serial read data 36bit serial cutoff read data read data 36bit serial 36bit serial 36bit serial figure 5. simplified application circuit autobahn 32bit data bus strb full r/w regsel ser ser logic (pal) serial bus oscillator fosc control signals data bus autobahn mc100sx1451 gnd note 3 v eex (20) v ee (8) v eet (3,11,18,30 36,43,51,59) gnd note 3 v cct (7,14,33,39, 47,55,63) gnd note 1 v cct (+5v) v cco (26) gnd 40pf v cce (+5v) 0.22 m f 0.22 m f 1 m h note 2 v ccx (22) gnd 40pf v cce (+5v) 0.22 m f note 1: capaitor located close to every pin. note 2: if separate supply planes for ecl and ttl are available, the inductor is not necessary. note 3: a common ground plane for ttl and ecl must be used. figure 6. power supply filtering application circuit and power supply address bus v cce (41) c1 v ccx c1 2700pf v cc (56)
mc100sx1451fi100 motorola eclinps and eclinps lite dl140 e rev 3 8 pecl design considerations the differential serial bus is realized using pecl (positive emitter coupled logic). pecl is normal ecl with the v cc and v ee power supplies levels shifted from ground and 5.2v to +5.0v and ground respectively. this change simplifies the requirements of interfacing high speed ecl circuitry and ttl circuitry on the same chip and improves the user system architecture because only a single power supply is required. the output driver circuitry is an open emitter, emitter follower which generates pecl levels when terminated by a pull down resistor to an appropriate reference voltage. the output emitter follower circuitry is optimized to drive transmission lines. to minimize line reflections, the transmission line should be terminated with the line characteristic impedance, in most cases 50 w . the simplest and most robust method of realizing this termination in pecl is with a resistor divider network referenced to v cc . this means the pecl output levels and the termination voltage will then be referenced to the same v cc supply. figure 8 is the equivalent circuit for the serial bus. resistors r1 and r2 are used to implement a simple voltage divider with the characteristic impedance of the transmission line. the following equations are used to solve for these values. r1 = r2 ({v cc v tt }/{v tt v ee }) r2 = z o ({v cc v ee }/{v cc v tt }) v tt = v cc (r2/{r1 + r2}) for the typical setup: v cc = 5.0v; v ee = gnd; v tt = 3.0v; and z o = 50 w r2 = 50 ({5 0}/{53}) = 125 w r1 = 125 ({53}/{30}) = 83.3 w more detailed information about pecl and thevenin equivalent termination schemes can be found in motorola application note an1406/d adesigning with peclo. figure 7. typical bus application parallel bus interface auto bahn card 1 parallel bus interface auto bahn card 2 parallel bus interface auto bahn card n traditional parallel bus differential bidirectional serial bus resistor divider termination network backplane figure 8. equivalent circuit for serial bus r2 r1 v cc r2 r1 v cc r2 r1 v cc r2 r1 v cc autobahn 1 autobahn n controlled impedance transmission lines
mc100sx1451fi100 eclinps and eclinps lite dl140 e rev 3 9 motorola control and error register bit definitions figure 9. control and error register definitions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 clear factory test factory test 16/32bit mode reserved write: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 clear factory test factory test 16/32bit mode reserved read: factory test factory test ignore timeout sync bit error word missing error error control factory test ignore timeout overwrite error factory test clear asserting this bit clears the internal control logic and terminates any transmit or receive activity. to remove the clear condition, this bit must be set to a logic `h' which sets the chip into the idle mode. h normal operation l clear 16/32 bit mode this bit defines the data width on the host interface. this feature allows the autobahn chip to be used in systems with either 16bit or 32bit data width without the need for additional interface hardware. in 16bit mode, the data bus used is d00 d15. h 32bit data width l 16bit data width factory test these bits are used by the manufacturer for testing the product. it must be set to a logic `h' state for proper operation. h normal operation ignore timeout this bit is used to disable the timeout timer for the transmitter. the purpose of this bit is to allow for the establishment of permanent or temporary dedicated links. when this bit is asserted, the timeout timer will be ignored by the piso control logic. this bit only needs to be set in the transmitting autobahn chip. to exit this mode, the control register must be accessed, and the field must be deasserted. h normal operation l disable timeout overwrite error flag this bit will be set if the data in the parallel register is overwritten. this can occur in receive mode if data is not read from the parallel register in a timely manner. the overwrite error does not occur in idle mode. h overwrite l no overwrite word missing error this bit will be asserted if the second half of a 32bit transfer is not completed before the time out timer expires. this can occur if the transmitter fails to complete the transfer. this field will be asserted only after the timeout timer expires. h word missing error l no error sync bit missing error this bit will be asserted if the autobahn detects that a sync bit has not been received at the proper time by the piso control logic. if this bit has been asserted then the data has been corrupted. h sync bit missing error l no error
mc100sx1451fi100 motorola eclinps and eclinps lite dl140 e rev 3 10 reserved bits all reserved bits are allocated for future enhancements. the user must write logic `h' values into these bits. reserved bits are read back as `do not care'. crystal oscillator requirements the autobahn requires a high quality frequency source (fosc) which is used as the reference for the pll clock generator. the performance requirements were targeted to provide the autobahn chip appropriate design margin for the serial data transfer operation as well as to allow the user flexibility is selecting a commercially available low cost crystal oscillator. below is a list of the key performance attributes of the crystal oscillator. parameter rating frequency 25.000mhz stability 100ppm output levels ttl duty cycle 45% / 55% at 1.5v rise/fall time 7nsec operating range 0 c to 70 c startup time 10msec there are many suppliers of high quality crystal oscillator frequency sources which meet or exceed the above requirements. one such supplier is jvc. their part numbers for 25mhz oscillators are as follows: vx43212500 (metal can) or smc2500 (smd). thermal considerations as in any system, proper thermal management is essential to establish the appropriate tradeoff between performance, density, reliability, and cost. in particular, the designer should be aware of the reliability implications of continuously operating semiconductor devices at high junction temperatures. the increasing use of surface mount devices (smd) is putting a greater emphasis on the need for better thermal system management. smd devices require less board space than their throughhole equivalents; so, designs incorporating smd technologies have a higher thermal density. to optimize the thermal management of the system, it is imperative that the user understand all the variables which contribute to the device junction temperature. by proper package selection, the vendor can select the proper package and die attach method to decrease the thermal resistance and thus the junction temperature of the device. the user has the greatest control of additional variables which commonly impact the thermal performance of the device. ambient temperatures, air flow, and related cooling techniques are obvious usercontrolled variables; however, pcb substrate material, layout density, size of the air gap between the board and the package, amount of exposed copper interconnect, use of thermally conductive epoxies, and the number of boards in a chassis can all have significant impacts on the thermal performance of the system. pcb substrates have different thermal characteristics which should be explored when considering alternatives. the user should also account for the different power dissipations of various components in the system and space them on the pcb accordingly. in this way the heat load is spread across a larger area and ahot spotso do not appear in the layout. copper interconnect traces act as heat radiators; therefore, improved thermal dissipation can be achieved through the addition of interconnect traces on the top layer. finally, thermally conductive epoxies can accelerate the transfer of heat from the device to the pcb where it can be more easily transferred to the ambient. the following equation can be used to estimate the junction temperature of a device in a given environment: t j = t a + p d *q ja t j junction temperature t a ambient temperature p d power dissipation q ja average package thermal resistance (junction ambient) the power dissipation is comprised of two elements: the internal gate power and the power associated with the output signals. essentially, the two contributors can be calculated separately, then added to give the total power dissipation for the device. the source of the output power distribution depends on whether the device is transmitting or receiving. in transmit mode, the pecl outputs are dissipating power, while in receive mode, the parallel outputs are dissipating dynamic power. the worst case condition, when the autobahn is in receive mode, is described below. p d = p static + p o (ttl) where pstatic = i cc * v cc v cc operating voltage i cc static dc current and po (ttl) = no* c l * f d * v s ^2 c l capacitive load (in pf) f d parallel data rate (0.5 * # mbits/sec) v s output swing no number of outputs (16 or 32)
mc100sx1451fi100 eclinps and eclinps lite dl140 e rev 3 11 motorola for a typical application: c l 20 pf f d 0.5* 100 mbits/s v s 3.8 v no 32 outputs v cc 5v i cc 700 ma p d = 470 * 5 + 32 * 20pf * 25 mhz*3.8 2 p d = 3.5 + 0.231w = 3.73w the ceramic quad flat package selected is manufactured from an aluminum nitride (aln) ceramic material for optimum thermal performance. a table of the average q ja values for this package under various air flow conditions is listed below: air flow (m/sec) q ja ( c/w) 0 40 1 32 2 23 with this information, the user can estimate the junction temperature of the device in their application. maximum ratings* symbol parameter value unit v cc power supply (v ee = 0v) 0.5 to 6.5 v v in input voltage (v ee = 0v) 0.5 to 6.5 v i out pecl output current continuous surge 50 100 ma i outttl ttl output current tbd t a operating temperature range 0 to 70 c t stg storage temperature range 50 to +175 c t j maximum junction temperature 175 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. ttl dc characteristics (v cct = v cc = v cco = 5.0v 5%) symbol parameter min typ max unit condition i ih input high current 0.7 m a v in = v cc i il input low current 0.6 ma v in = gnd v oh output high voltage 2.5 v i oh = 2ma v ol output low voltage 0.5 v i ol = 5.0ma v ih input high voltage 2.0 v v il input low voltage 0.8 v i oz tristate current 15 m a i cc device current drain 700 760 ma 100e pecl dc characteristics (v cct = v cc = v cco = 5.0v 5%) symbol parameter min max unit condition i ih input high current 200 m a i il input low current 0.500 m a v oh output high voltage 3.975 4.25 v v cut output cutoff voltage 3.000 3.07 v note 1. v ih input high voltage 3.835 4.12 v v il input low voltage 3.000 3.07 v v pp (dc) input sensitivity 150 mv note 2. note: pecl levels are referenced to v cc and will vary 1:1 with power supply. the outputs are loaded with an equivalent 25 w termination to +3.0v. the values shown are for v cc = v cco = v cct = 5.0v. 1. valid when the equivalent termination voltage is 3.0v to assure proper operation. 2. v pp is the minimum differential input voltage required to assure proper operation.
mc100sx1451fi100 motorola eclinps and eclinps lite dl140 e rev 3 12 ac characteristics (v cc = v cco = v cct = 5.0v 5%; v ee = v eex = v eet = gnd) name wave 0 c 25 c 70 c symbol characteristic n ame form min typ* max min typ* max min typ* max unit condition t s setup time r/w strb regsel strb data strb t2 2 1.0 1.0 1.0 ns t h hold time strb r/w strb regsel t3 2 3.0 3.0 3.0 ns t pd propagation delay strb full t4 2 4.0 6.0 9.0 4.0 6.0 9.0 4.0 6.0 9.0 ns t h hold time strb data t5 2 3.0 3.0 3.0 ns t pd propagation delay ser busy t6 3 6.0 8.0 10.0 6.0 8.0 10.0 6.0 8.0 10.0 ns t s setup time r/w strb regsel strb t7 4 2.0 2.0 2.0 ns t h hold time strb r/w strb regsel t8 4 1.0 1.0 1.0 ns t pd propagation delay strb data valid t9 4 7.0 8.5 18.0 7.0 8.5 18.0 7.0 8.5 18.0 ns note 1 on page 13 t pd propagation delay strb full t10 4 5.5 8.0 10.0 5.5 8.0 10.0 5.5 8.0 10.0 ns note 1 on page 13 t pd propagation delay strb data invalid t11 4 12.0 14.0 17.0 12.0 14.0 17.0 12.0 14.0 17.0 ns note 1 on page 13 t s setup time r/w strb regsel strb data strb t12 5 1.0 1.0 1.0 ns t h hold time strb r/w strb regsel t13 5 3.0 3.0 3.0 ns t h hold time strb data t14 5 3.0 3.0 3.0 ns t pw pulse width strb t15 5 7.0 12.0 7.0 12.0 7.0 12.0 ns t s setup time r/w strb regsel strb t16 6 2.0 2.0 2.0 ns t h hold time strb r/w strb regsel t17 6 2.0 2.0 2.0 ns t pd propagation delay strb data valid t18 6 7.0 8.5 18.0 7.0 8.5 18.0 7.0 8.5 18.0 ns t pw pulse width strb t19 6 7.0 12.0 7.0 12.0 7.0 12.0 ns t pd propagation delay strb data invalid t20 6 14.0 17.0 14.0 17.0 14.0 17.0 ns t r , t f ttl rise/fall time e e 3.0 6.1 12.6 3.0 ns 10 90% 15pf load t r , t f pecl rise/fall time e e 200 770 930 200 ps 20 80% * values for 0 c and 70 c are target values. typicals for 25 c are taken from a small measurement database. min and max values are derived from using 3 sigmas point of the data distribution and will be added when the data becomes available.
mc100sx1451fi100 eclinps and eclinps lite dl140 e rev 3 13 motorola note 1: propagation delay t9 becasue the typical use of the autobahn is in a shared bus system, the propagartion delay t9 (strb > data valid) is the time between the falling edge of strb and output active of the receiver. the crosspoint of 1.5v is dependent on the bus environment. see figure 10. propagation delay t10 this value is taken with the high impedance active probe. with a higher load at the pin, this value will be higher up to 5%. propagation delay t11 the definition of the propagation delay t11 corresponds to t9. in this case, t11 is the time between the rising edge of strb and the high impedance of the receiver. that means, other talker of the common bus have to wait for t11 to send datas to the bus. see figure 10. t9 t11 output active high z high z figure 10. definition of the waveforms strb data valid data strb 1.5v 0v load c=15pf r=1k w timing waveforms strb (i) ser (o) ser (o) t1 1.5v 50% waveform 1. start of transmit timing d00:d31 (i) r/w (i) 1.5v 1.5v regsel (i) 1.5v 1.5v strb (i) 1.5v full (o) 1.5v high z data valid 1 1.5v high z 1 t4 t3 t2 t5 waveform 2. transmit mode data transfer handshake note 2: t1 (strb to ser differential) is indeterminate, varying from 3 to 9 bit clock cycles due to synchronization circuitry to avoid metastability. note 3 note 3: strb deassertion to next full a minimum of 18 nsec.
mc100sx1451fi100 motorola eclinps and eclinps lite dl140 e rev 3 14 ser (i) 50% ser (i) busy (o) t6 1.5v waveform 3. timing for detection of a steadystate differential condition on the serial bus r/w (i) 1.5v 1.5v regsel (i) 1.5v 1.5v d00:d31 (i) data valid 1 high z 1 strb (i) 1.5v full (o) 1.5v t8 t7 t9 t10 t11 waveform 4. receive mode data transfer handshake d00:d31 (i) r/w (i) 1.5v 1.5v regsel (i) 1.5v 1.5v strb (i) 1.5v high z data valid 1 1.5v high z 1 t13 t15 waveform 5. write to control register 1.5v t12 t14 r/w (i) 1.5v 1.5v regsel (i) 1.5v 1.5v d00:d31 (i) data valid 1 high z 1 strb (i) 1.5v t17 t16 t18 t19 t20 waveform 6. read from the control and error registers
mc100sx1451fi100 eclinps and eclinps lite dl140 e rev 3 15 motorola r/w reset error d10 d11 veet d12 d13 d14 vcct vcc d15 d16 veet d17 d18 d19 vcct d20 full veet regsel vcco ser vccx fosc veex c1 veet d09 vcct d08 d07 d06 veet d05 vcce d04 vcct d03 d02 veet d01 d00 vcct d21 d22 veet d23 d24 d25 vcct vee d26 d27 veet d28 d29 vcct d30 d31 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 12345678910111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 mc100sx1451 figure 11. pinout: 64lead cqfp (top view) ser strb busy
mc100sx1451fi100 motorola eclinps and eclinps lite dl140 e rev 3 16 fi suffix ceramic qfp package case 96302 issue a outline dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane h. 5. dimensions s and v to be determined at seating plane c. 6. dimensions a and b define maximum ceramic body dimension including glass protrusion and mismatch between ceramic body and cover. dim a min max min max inches 13.90 14.10 0.547 0.555 millimeters b 13.90 14.10 0.547 0.555 c 3.00 4.11 0.118 0.162 d 0.30 0.45 0.012 0.018 e 2.54 3.22 0.100 0.127 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h 0.45 0.89 0.018 0.035 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 12.00 ref 0.472 ref n 0.13 0.17 0.005 0.007 p 0.40 bsc 0.016 bsc q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 16.95 17.45 0.667 0.687 t 0.13 0.005 u 0 0 v 16.95 17.45 0.667 0.687 w 0.35 0.45 0.014 0.018 x 1.60 ref 0.063 ref l l b v a s g h e c seating plane 0.01 (0.004) detail c detail a q u x t r w k datum plane detail c 1 16 17 32 33 48 49 64 a b h datum plane c d h b b p detail a d f j n view rotated 90 clockwise section bb base metal a, b, d s ab m 0.02 (0.008) d s c s ab m 0.20 (0.008) d s c ab 0.05 (0.002) s ab m 0.20 (0.008) d s h s ab m 0.20 (0.008) d s c ab 0.05 (0.002) s ab m 0.20 (0.008) d s h
mc100sx1451fi100 eclinps and eclinps lite dl140 e rev 3 17 motorola motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mc100sx1451fi100/d ? mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.: spd, strategic planning office, 4321, p.o. box 5405, denver, colorado 80217. 3036752140 or 18004412447 nishigotanda, shinagawaku, tokyo 141, japan. 81354878488 mfax ? : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 internet : http://motorola.com/sps

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